1. Field of the Invention
The present invention relates to a method for manufacturing a nonvolatile memory device, and more particularly, to a method for manufacturing a nonvolatile memory device capable of preventing damage to side walls of a stacked gate and active region.
2. Description of the Related Art
In order to attain a highly integrated nonvolatile memory device, various researches into a technology for reducing the cell size in a word line direction and a bit line direction have been carried out. An example of the technology, a so-called self-aligned source etching technology is disclosed in U.S. Pat. No. 5,120,671, by which limitations in reducing the cell size due to the presence of an active region in which a source line diffusion layer for connecting source regions of neighboring cells in a word line direction are solved. In other words, instead of forming the active region for forming the source line diffusion layer, a field oxide layer is etched to form the source line diffusion layer under the field oxide layer, thereby connecting source regions of neighboring cells in a word line direction. According to the self-aligned source etching technology, since an active region for forming a source line diffusion layer is not necessary for an insulation distance between the word line and active region where the source line diffusion layer will be formed is necessary, the size of a memory cell array can be reduced.
According to the self-aligned source etching process, first, a stacked gate structure is formed on a substrate where a field oxide layer has been formed. The stacked gate structure comprises a gate oxide layer, a floating gate, a dielectric layer and a control gate which are sequentially stacked. Next, a mask for exposing source regions of neighboring cells in a direction of the control gate which functions as a word line. Subsequently, the field oxide layer exposed by the mask is etched using the word line as a self-align mask and impurities are implanted thereinto to form a source line diffusion layer for connecting the source regions of neighboring cells.
During the self-aligned source etching process, the side walls of the stacked gate structure close to the source regions are exposed to the self-aligned source etch. Thus, the gate oxide layer, the floating gate, the intergate dielectric layer, some the control gate and the substrate are subject to etching damage. Particularly, the gate oxide layer and the intergate dielectric layer are severely damaged, which degrades the characteristics of a nonvolatile memory device.
Also, during the self-aligned source etching process, the active region where the source region is formed is etched as well as the field oxide layer. In other words, a silicon substrate of the active region is over-etched 300 .ANG. or more, which causes etching damage to the source region. If the etching damage is generated, a charge retention capability is reduced. To solve the etching damage, annealing may be adopted. However, the annealing, which must be performed at a high temperature of 900-1000.degree. C., creates another problem.
To avoid such etching damage, a technology for forming a spacer at side walls of a stacked gate structure prior to the self-aligned source etching process is disclosed in U.S. Pat. No. 5,470,773. If the spacer is formed according to this method, the damage problem of the side walls of the stacked gate stricture can be solved. However, the damage problem of the active region is yet to be solved. Also, two-step processes are further necessary for forming the spacer, that is, one step of forming a dielectric layer for a spacer, and another step of forming the dielectric layer as a spacer by anisotropically etching the same.